Course Curriculum
Total learning: 137 lessons Time: 100 weeks
- Number system 27
- Number System introductionLecture1.1
- Number System Conversion ( Decimal to Others )Lecture1.2
- Number System Conversion ( Others to Others )Lecture1.3
- Number System Conversion ( Others to Others )Lecture1.4
- Weighted Number SystemLecture1.5
- Binary Number SystemLecture1.6
- Binary to Octal conversionLecture1.7
- Number System TypesLecture1.8
- Number System Conversion ProblemsLecture1.9
- Binary Arithmetical operations ( addition )Lecture1.10
- Binary Arithmetical operations ( SUB )Lecture1.11
- Binary multiplication and divisionLecture1.12
- BCD (Binary Coded Decimal ) CodeLecture1.13
- BCD ConversionLecture1.14
- Excess – 3 Code ConversionLecture1.15
- Gray codeLecture1.16
- Binary to Gray conversionLecture1.17
- Compliments of number systemLecture1.18
- Problems on Binary number systemLecture1.19
- Binary Data RepresentationLecture1.20
- Unsigned and Signed Binary Data RepresentationLecture1.21
- 1’s compliment binary data representationLecture1.22
- 2’s compliment binary data representationLecture1.23
- Problems on Binary Data RepresentationLecture1.24
- Floating Point Binary Data RepresentationLecture1.25
- Assignment – 1Lecture1.26
- Assignment – 1_SolutionsLecture1.27
- Boolean Algebra 8
- IntroductionLecture2.1
- Boolean AlgebraLecture2.2
- De-Morgan’s TheoremLecture2.3
- Boolean Algebra( Canonical Form)Lecture2.4
- Boolean Algebra( Canonical Form) – 01Lecture2.5
- Boolean Algebra( Consensus OR Redundancy Theorem)Lecture2.6
- Boolean Algebra( Duality Theorem)Lecture2.7
- Boolean Theorems (All)Lecture2.8
- Boolean Theorems - 02 5
- SOP AND POS ( Boolean expression representation)Lecture3.1
- SOP AND POS – 2 ( Boolean expression representation)Lecture3.2
- Logic Gates( special)Lecture3.3
- Logic Gates( basic gates)Lecture3.4
- Logic Gates ( universal gates)Lecture3.5
- Logic Gates 11
- Logic GatesLecture4.1
- Logic Gates- 01Lecture4.2
- Logic Gates -( Bubbled Gates)Lecture4.3
- NOR – NOR logicLecture4.4
- Logic Gates using NAND and NOR GatesLecture4.5
- Digital Circuits Using NAND GatesLecture4.6
- Digital Circuits Using NAND Gates-01Lecture4.7
- Basic Gates using DiodesLecture4.8
- AssignmentLecture4.9
- assignment_contLecture4.10
- Assignment_SolutionsLecture4.11
- K - MAP 8
- K- MAP InroductionLecture5.1
- K-MapLecture5.2
- 2 – VARIABLE K – MAPLecture5.3
- 3 – VARIABLE K – MAP_1Lecture5.4
- 3 – variable K-Map problemsLecture5.5
- 3 – variable K-Map with don’t care combinationsLecture5.6
- 3 – variable K-Map problemsLecture5.7
- 4 – Variable K-MapLecture5.8
- Introduction 8
- IntroductionLecture6.1
- Introduction to Digital CircuitsLecture6.2
- Half adder and Procedure to design combinational circuitsLecture6.3
- Half adder using NAND and NOR GatesLecture6.4
- Half SubtractorLecture6.5
- Full AdderLecture6.6
- Full Adder using NAND gatesLecture6.7
- Full SubtractorLecture6.8
- Parallel Adders and Subtractors 6
- Parallel AdderLecture7.1
- Parallel SubtractorLecture7.2
- Parallel Adder/SubtractorLecture7.3
- Delay of Parallel AdderLecture7.4
- Look Ahead Carry AdderLecture7.5
- Look Ahead Carry Adder – 1Lecture7.6
- MULTIPLEXER and De-MULTIPLEXER 8
- Multiplexer introduction and 2:1 MUXLecture8.1
- Design of all gates using MUXLecture8.2
- 4:1 MultiplexerLecture8.3
- Problems on MultiplexersLecture8.4
- Problems on Multiplexers-1Lecture8.5
- 4:1 MUX and 8:1 MUX using 2:1 MUXLecture8.6
- 16:1 MUX using 4:1 MUXLecture8.7
- De-MultiplexerLecture8.8
- DECODERS AND ENCODERS 9
- Decoders ( 2:4 Decoders)Lecture9.1
- 3 : 8 Decoder and Active Low output DecoderLecture9.2
- Design of combinational circuit using decodersLecture9.3
- Design of combinational circuit using decoders1Lecture9.4
- D4 : 16 decoder using 2 : 4 decoderLecture9.5
- ENCODERS ( 4 : 2 Encoder)Lecture9.6
- Priority EncoderLecture9.7
- Comparator Digital CircuitLecture9.8
- Comparator Digital Circuit -1Lecture9.9
- SEQUENTIAL CIRCUITS 12
- IntroductionLecture10.1
- LATCH Circuit and OperationLecture10.2
- NAND LatchLecture10.3
- NOR LatchLecture10.4
- NOR Latch – 1Lecture10.5
- Set-Reset (SR) Flip FlopLecture10.6
- Set-Reset (SR) Flip Flop – 1Lecture10.7
- J K Flip FlopLecture10.8
- J K Flip Flop – 1Lecture10.9
- J K Flip Flop – 2Lecture10.10
- T-FF (TOGGLE FLIP FLOP )Lecture10.11
- Delay Flip Flop ( D-FF)Lecture10.12
- Flip Flop Conversion 7
- FLIP FLOP CONVESION ( JK-FF TO D-FF)Lecture11.1
- D-FF to others ( D-FF to J K, T )Lecture11.2
- SR-FF to JK-FF and D-FF to T-FF CONVERSIONLecture11.3
- T-FF TO JK-FF CONVERSIONLecture11.4
- TRIGGERING (CLOCK SIGNAL)Lecture11.5
- TRIGGERING (CLOCK SIGNAL)Lecture11.6
- RACE AROUND CONDITION ( RAC ) AND MASTER-SLAVE JK FFLecture11.7
- COUNTERS 9
- INTRODUCTION ( COUNTERS)Lecture12.1
- ASYNCHRONOUS COUNTERS ( 2-BIT RIPPLE COUNTER)Lecture12.2
- 2-BIT RIPPLE COUNTER USING +VE AND -VE EDGE TRIGGERINGLecture12.3
- IMPORTANT POINTS FROM ASYNCHRONOUS COUNTERSLecture12.4
- 3 – bit ripple counter ( MOD – 8 Ripple Counter)Lecture12.5
- MOD – K Counter and Asynchronous inputs of flip flopLecture12.6
- (MOD-10)Modulus 10 Counter ( Decade counter)Lecture12.7
- UP/DOWN CounterLecture12.8
- Problems on Asynchronous CounterLecture12.9
- SYNCHRONOUS COUNTERS and REGISTERS 13
- Introduction to Synchronous CountersLecture13.1
- Ring CounterLecture13.2
- TWISTED RING COUNTER( JOHNSON COUNTER)Lecture13.3
- DESIGN OF SYNCHRONOUS COUNTERLecture13.4
- MOD – 6 BINARY COUNTER( SYNCHRONOUS) USING T-FFLecture13.5
- SELF STARTING RING COUNTERLecture13.6
- REGISTERSLecture13.7
- SISO( Serial Input Serial Output)Lecture13.8
- TYPES OF REGISTERS(SIPO,PIPO,PISO)Lecture13.9
- UNIVERSAL SHIFT REGISTERLecture13.10
- UNIVERSAL SHIFT REGISTER – 1Lecture13.11
- Problems on countersLecture13.12
- Problems on counters – 1Lecture13.13
- STATE DIAGRAMS 6
- INTRODUCTION TO STATE DIAGRAMSLecture14.1
- MEALY AND MOORE DIAGRAMSLecture14.2
- STATE DIAGRAMS OF FLIPFLOPSLecture14.3
- STATE DIAGRAMS OF FLIPFLOPS-1Lecture14.4
- PROBLEMS ON STATE DIAGRAMSLecture14.5
- PROBLEMS ON STATE DIAGRAMS-1Lecture14.6
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